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Instruction Set Architecture
GPL ISA Reference
The 8-instruction phase-aware instruction set: opcodes, operand encoding, the assembler, the disassembler, and example GPL assembly programs.
The GPL ISA is a minimal 16-bit instruction set designed to operate over the four phase states. Every instruction is phase-aware: operands are phase registers, and the ALU performs compose (∘) rather than binary arithmetic.
Instruction Set
| Mnemonic | Opcode | Operands | Description |
|---|---|---|---|
| LOAD | 0x00 | reg, state | Load a phase state into a register |
| STORE | 0x01 | reg, addr | Store a register value to memory |
| COMP | 0x02 | dst, src1, src2 | Compose two registers: dst ← src1 ∘ src2 |
| JMP | 0x03 | addr | Unconditional jump to address |
| JMPZ | 0x04 | reg, addr | Jump if register equals Φ0 (zero/ground state) |
| HALT | 0x05 | none | Halt execution and return to kernel |
| NOP | 0x06 | none | No operation — advance program counter |
| SYS | 0x07 | call_id | System call — transfer control to Φ3 (kernel) |
Instruction Encoding
Instructions are 16 bits wide. Bits 15–12 encode the opcode (4 bits, supporting up to 16 instructions). Bits 11–8 encode the destination register. Bits 7–0 encode the source operands or immediate value.
[15:12] opcode | [11:8] dst | [7:4] src1 | [3:0] src2/immAssembler & Disassembler
The GPL assembler translates human-readable assembly text into binary machine code. The disassembler reverses the process. Both are included in the isa/ module.
Example program
; Load Φ1 (ready) into r0 LOAD r0, Φ1 ; Load Φ2 (running) into r1 LOAD r1, Φ2 ; Compose: r2 ← r0 ∘ r1 COMP r2, r0, r1 ; System call to kernel SYS 0 HALT